1. Field of the Invention
The present invention relates to a memory testing apparatus for testing various kinds of semiconductor memories including a memory being constructed by, for example, a semiconductor integrated circuit (hereinafter, referred to as IC), and more particularly, to an improvement in a memory testing apparatus provided with a failure relief analyzer for counting the number of failure memory cells of a tested semiconductor memory to determine whether the relief of the tested semiconductor memory can be carried out or not. (Hereinafter, a memory being constructed by a semiconductor integrated circuit is referred to as IC memory.)
2. Description of the Related Art
Recently, storage capacity of an IC memory is increasing more and more, and accordingly an increased IC chip area and formation of patterns at high density are required. As a result, there is an increased possibility that a reduction of the yield of IC memories caused by a very minute defect occurs. In order to prevent the yield of IC memories from being reduced, there are manufactured IC memories in each of which, for example, one or more failure memory cells can be electrically replaced by a substitute or alternative memory cell (also called a spare line, relief line or redundancy circuit). As will be described later, the IC memory of this kind is called a memory of redundancy structure in this technical field, and a decision as to whether the redundancy-structured memory can be relieved or not is rendered by a failure relief analyzer.
FIG. 2 shows a block diagram of a general construction of an example of the prior memory testing apparatus having a conventional failure relief analyzer. As is well known, this memory testing apparatus comprises a timing generator 10, a pattern generator 20, a waveform shaping device 30, a logical comparator 40, a failure analysis memory 50 and a failure relief analyzer 6. Further, in the following description, a case that the memory testing apparatus will test IC memories will be described. In case of testing various kinds of semiconductor memories other than IC memories by the memory testing apparatus, however, they will be tested in similar manner.
The timing generator 10 generates a clock CLK constituting a reference for the entire memory testing apparatus and various timing signals (not shown). Based on (in synchronism with) the reference clock CLK supplied from the timing generator 10, the pattern generator 20 generates address data ADRD, test pattern data PTND and control data CNTLD all of which are to be supplied to an IC memory under test (hereinafter, simply refereed to as memory under test) MUT. These data signals are inputted to the waveform shaping device 30 where they are converted, on the basis of timing signals (not shown) supplied from the timing generator 10, into an address signal ADR, a test pattern signal PTN and a control signal CNTL, respectively, having real waveforms required for testing the memory under test MUT. Thereafter, these signals are applied to the memory under test MUT.
The read/write operations of the memory under test MUT are controlled by the control signal CNTL supplied thereto through the waveform shaping device 30 so that a writing of the test pattern signal PTN applied from the waveform shaping device 30 in the memory under test and a reading of the written test pattern signal can be performed. The test pattern signal PTN written in the memory under test MUT is read out therefrom later, and the read-out response signal RPD is supplied to the logical comparator 40 where the response signal RPD is logically compared with an expected value pattern data (signal) EXP supplied from the pattern generator 20 to detect whether or not there is an anticoincidence between the two signals.
If the two signals do not coincide with each other, the logical comparator 40 determines that the memory cell having an address of the memory under test MUT from which the response signal RPD has been read out is defective (failure), and generates a failure signal FAIL indicating that fact. When the failure signal FAIL is generated from the logical comparator 40, usually, a logical xe2x80x9c1xe2x80x9d signal (data) is stored in a memory cell of the failure analysis memory 50 specified by address data ADRD (in practice, an address signal ADR obtained by converting this address data into a physical address) from the pattern generator 20. In general, this logical xe2x80x9c1xe2x80x9d signal is stored in the same address of the failure analysis memory 50 as that of the failure memory cell of the memory under test MUT.
On the contrary, if the response signal RPD coincides with the expected value pattern data EXP, the logical comparator 40 determines that the memory cell having an address of the memory under test MUT from which the response signal RPD has been read out is not defective (pass), and generates a pass signal indicating that fact. This pass signal is not stored in the failure analysis memory 50.
In such a way, the information on the failure memory cells (logical xe2x80x9c1sxe2x80x9d) of the memory under test MUT generated during a series of tests is stored in the failure analysis memory 50. After the testing has been completed, the failure data stored in the failure analysis memory 50 are read out therefrom into the failure relief analyzer 6, thereby to carry out a failure analysis for the memory under test MUT.
The failure analysis memory 50 has its operating rate or speed and its memory capacity equivalent to those of the memory under test MUT, and the same address signal as the address signal ADR applied to the memory under test is also applied to this failure analysis memory 50. In addition, the failure analysis memory 50 is initialized prior to the start of a testing. For example, when initialized, the failure analysis memory 50 has data of logical xe2x80x9c0sxe2x80x9d written in all of the addresses thereof. Every time a failure signal FAIL indicating the anti-coincidence is generated from the logical comparator 40 during a testing of a memory under test MUT, a failure data of logical xe2x80x9c1xe2x80x9d indicating the failure of a memory cell is written in the same address of the failure analysis memory 50 as that of the memory cell of the memory under test MUT from which that anti-coincidence has been generated.
The failure relief analyzer 6 separately and simultaneously counts the total number of failure memory cells stored in the failure analysis memory 50, and the number of failure memory cells on each address line of row (lateral) address lines and column (longitudinal) address lines stored in the failure analysis memory 50, and analyzes to determine whether the relief of the tested memory can be done or not by use of relief lines, i.e., spare memory cells (spare lines or redundancy circuits) provided in the memory under test MUT. A memory having such relief lines provided therein is, as mentioned above, called a redundancy-structured memory in this technical field.
Here, a brief explanation will be given regarding a redundancy-structured memory. FIG. 3 shows in outline an arrangement of an example of such redundancy-structured memories. A memory under test MUT is provided with, in addition to a memory cell array (main storage portion) MCA where memory cells are arrayed in rows and in columns, row address relief lines SR and column address relief lines SC formed on the periphery of the memory cell array MCA. The memory cell array MCA, the row address relief lines SR and the column address relief lines SC are formed in the same semiconductor chip. In this example, a case is shown where two row address relief lines SR are disposed along one side of the row address direction of the memory cell array MCA and two column address relief lines SC are disposed along one side of the column address direction of the memory cell array MCA, respectively. However, it is needless to say that the number of relief lines and the positions where these relief lines are disposed are not limited to the example as illustrated.
As a result of the testing of the memory under test MUT, in case that three failure memory cells X1, X2 and X3 are detected, for example, on the i-th row address line Ri (i is an integer) and three failure memory cells Y1, Y2 and Y3 are detected, for example, on the i-th column address line Ci (i is an integer), if the row address line Ri is substituted by any one of the row address relief lines SR with respect to its electrical connection, the row address line Ri having the failure memory cells can be relieved. Similarly, if the column address line Ci is substituted by any one of the column address relief lines SC with respect to its electrical connection, the column address line Ci having the failure memory cells can also be relieved.
In such a way, the redundancy-structured memory is arranged such that failure memory cells in its memory cell array MCA can be relieved by its row and column address relief lines. Therefore, by counting the number of failure memory cells of each row address line and the number of failure memory cells of each column address line and by comparing the number of row and column address lines each having failure cells with the number of relief lines, a decision can be rendered as to whether the memory cell array MCA can be relieved or not.
For this reason, as shown in FIG. 4, in the conventional failure relief analyzer 6 the number of failure memory cells in each row address line within the memory cell array MCA is counted by a row address failure counter (RFC) 3 and the number of failure memory cells in each column address line within the memory cell array MCA is counted by a column address failure counter (CFC) 4, and in addition, the total number of failure memory cells are counted by a total failure counter (TFC) 81. Then, based upon these counted values, the possibility of relief of the memory cell array MCA is determined.
Further, the row address failure counter 3 and the column address failure counter 4 are, in practice, constructed such that they count the number of failure data representing failure memory cells on each of the row address lines and the number of failure data representing failure memory cells on each of the column address lines read out from the failure analysis memory 50, respectively, and store the counted values in their failure storing memories. The total failure counter 81 is constructed such that it accumulates, every time a failure data is read out from the failure analysis memory 50, the number of occurrences of the failure data, and stores the accumulated value in a total failure storing memory of the total failure counter 81.
An actual analysis in the failure relief analyzer 6 as to whether the memory under test MUT can be relieved or not is carried out by dividing, as shown in FIG. 5, the memory cell array MCA into several ten to several thousand relief blocks B, and for each of the divided relief blocks B. Therefore, the counting operations of the number of failure memory cells (the number of failure data) in the total failure counter 81, the row address failure counter 3 and the column address failure counter 4 are performed for each of the divided relief blocks, respectively. In this case, the counting operation of the number of failure data is carried out such that the stored content of the failure storing memory of each counter is read out therefrom, and the read-out value is incremented by one, which is stored back in each failure storing memory if the read-out data from the failure analysis memory 50 is xe2x80x9c1xe2x80x9d (if a failure data is read out), or the read-out value is maintained as it is, and is stored back in each failure storing memory if a failure data is not read out from the failure analysis memory 50. Therefore, each of the failure storing memories for storing therein the counted value of the number of failure data must be initialized without fail prior to performing the counting operation of the number of failure data for each relief block B.
In FIG. 5, relief blocks to which o is affixed show relief blocks in which any failure memory cell has not been detected, and relief blocks to which x is affixed show relief blocks in which one or more failure memory cells have been detected. In addition, since the failure relief analysis for a memory under test is performed for each relief block basis, a block address for specifying each relief block is necessary. In FIG. 5, reference characters #0, #1, #2, . . . , #1F affixed to the respective relief blocks show block addresses, respectively. The number of failure memory cells counted for each of the relief blocks is stored in a memory cell of a block failure memory BFM having the same address as the corresponding block address.
In recent years, a memory under test is increasing more and more in its memory capacity, and the number of relief blocks and the size tend to be increased. Associated with this fact, the capacity of each of the failure storing memories for storing therein the counted value of the number of failure memory cells is also increased. For this reason, there has been a problem that it takes a long time to initialize these failure storing memories, and hence a time duration required for the failure relief analysis of a memory under test becomes long. Accordingly, it has been requested that a time duration needed to initialize the data stored in these failure storing memories is reduced, and the failure relief analysis can be carried out at high speed.
It is an object of the present invention to provide a memory testing apparatus provided with a failure relief analyzer, which is capable of carrying out a failure relief analysis for a redundancy-structured memory at high speed.
It is another object of the present invention to provide a memory testing apparatus provided with a failure relief analyzer, which need not initialize, prior to counting the number of failure data representing failure memory cells of a memory under test, failure storing memories for storing therein counted values of the number of failure data.
In order to accomplish the aforesaid objects, in one aspect of the present invention, there is provided a memory testing apparatus which comprises: a failure analysis memory for storing therein failure data representing a failure memory cell of a memory under test; and failure relief analyzer for carrying out a failure relief analysis for a tested memory on the basis of failure data stored in the failure analysis memory, the failure relief analyzer comprising: a failure storing memory for storing therein the number of failure data read out from the failure analysis memory; and an output altering circuit for outputting the value of read-out data read out at the first time from each address of the failure storing memory as xe2x80x9c0xe2x80x9d.
The output altering circuit is constituted by an initialization controller for generating an initialization signal when data is read out at the first time from each address of the failure storing memory; and a data controller for outputting an output of the failure storing memory as it is in the case that the initialization signal does not come to the data controller from the initialization controller and outputting xe2x80x9c0xe2x80x9d in the case that the initialization signal comes to the data controller from the initialization controller.
In one preferred embodiment, the aforesaid failure storing memory for storing the number of failure data read out from the failure analysis memory is a row failure storing memory provided in a row address failure counter for counting the number of failure data for each row address line of the failure analysis memory, a column failure storing memory provided in a column address failure counter for counting the number of failure data for each column address line of the failure analysis memory and a total failure storing memory provided in a total failure counter for counting the total number of failure data.
In addition, the aforesaid output altering circuit is constituted by an initialization controller for applying an initialization signal to the row address failure counter when a row counter address signal for accessing the row failure storing memory is xe2x80x9c0xe2x80x9d, applying an initialization signal to the column address failure counter when a column counter address signal for accessing the column failure storing memory is xe2x80x9c0xe2x80x9d and applying an initialization signal to the total failure counter when both of the row counter address signal and the column counter address signal are xe2x80x9c0xe2x80x9d; and data controllers provided respectively in the failure counters, each data controller outputting an output read out from the associated failure storing memory as it is in the case that the initialization signal is not applied thereto from the initialization controller and outputting xe2x80x9c0xe2x80x9d in the case that the initialization signal is applied thereto from the initialization controller.
The aforesaid failure relief analyzer further comprises: a TFC address formatter for formatting a total failure counter address signal for accessing the total failure storing memory of the total failure counter on the basis of row address data and column address data inputted thereto, and outputting the formatted address signal; an RFC address formatter for formatting a row failure counter address signal for accessing the row failure storing memory of the row address failure counter on the basis of row address data and the total failure counter address signal inputted thereto, and outputting the formatted address signal; a CFC address formatter for formatting a column failure counter address signal for accessing the column failure storing memory of the column address failure counter on the basis of column address data and the total failure counter address signal inputted thereto, and outputting the formatted address signal. The initialization controller produces the initialization signal on the basis of the row failure counter address signal supplied from the RFC address formatter and the column failure counter address signal supplied from the CFC address formatter, and the row address failure counter, the column address failure counter and the total failure counter include respective adders each adding an output of corresponding one of the failure analysis memories to an output of corresponding one of the data controllers and supplying the result of addition to corresponding one of the row failure storing memory, the column failure storing memory and the total failure storing memory.